The Semiconductor Race: The Geopolitics of Silicon

Zusammenfassung

This article traces the history of semiconductor manufacturing from the early days of the integrated circuit to the physical limits of Moore’s Law — and the geopolitical crisis those limits have produced. It is the story of how a Taiwanese engineer named Morris Chang built the world’s most strategically indispensable company, how a Dutch firm became the sole manufacturer of the machines that make advanced chips possible, and why the fate of the global technology industry depends on the stability of a single island of roughly 36,000 square kilometers.

Moore’s Law as Industrial Roadmap

In 1965, Gordon Moore — co-founder of Fairchild Semiconductor, later of Intel — observed that the number of transistors on an integrated circuit had roughly doubled every year since the first ICs appeared in 1959. He predicted this trend would continue for at least ten more years.

It continued for fifty.

Moore’s Law was not a law of physics. It was an observation about economic and engineering incentives: the semiconductor industry had organized itself to deliver a doubling of transistor density approximately every two years, because the competitive rewards for doing so were enormous. Each generation of chips was smaller, faster, and cheaper per transistor than the last. The personal computer, the smartphone, the cloud datacenter — all depend on this compounding.

The unit of progress in semiconductor manufacturing is the process node — loosely, the smallest feature size that can be reliably fabricated. In 1971, Intel’s first microprocessor used a 10-micrometer (10,000 nm) process. By 2024, the leading edge was 3 nm — a dimension at which individual transistors are measured in atoms. A modern processor contains tens of billions of transistors — the largest now exceeding the roughly 86 billion neurons in the human brain.

Morris Chang and the Invention of the Foundry

Through the 1970s and 1980s, semiconductor companies were Integrated Device Manufacturers (IDMs): they designed chips and built them in their own factories (fabrication plants, or “fabs”). Intel, Texas Instruments, Motorola, NEC — each vertically integrated from silicon wafer to finished product. Building and operating a fab required billions of dollars and thousands of specialized engineers, which limited the industry to companies large enough to sustain that investment.

Morris Chang had spent years at Texas Instruments before joining the Industrial Technology Research Institute in Taiwan. In 1987, with backing from the Taiwanese government, he founded Taiwan Semiconductor Manufacturing Company (TSMC) in Hsinchu. Its model was novel: TSMC would manufacture chips designed by other companies, owning no designs of its own. It would be a pure-play foundry.

The model solved a structural problem in the industry. Designing a chip and manufacturing a chip required completely different skills and capital. TSMC allowed companies to focus exclusively on design — fabless semiconductor companies — while outsourcing the manufacturing. Qualcomm, ARM, AMD (after spinning off its fabs), Broadcom, NVIDIA: none of these companies own fabs. They design silicon and give the designs to TSMC.

TSMC’s incentives were also different from an IDM. It had no reason to favor one customer’s design over another’s, and every reason to advance manufacturing technology: its business depended on being ahead of what customers could build themselves. Through the 1990s and 2000s, TSMC invested aggressively in process technology, and by the 2010s it had pulled ahead of all but Intel in manufacturing capability. By the early 2020s, TSMC manufactured chips for Apple, NVIDIA, AMD, Qualcomm, and — critically — the advanced logic chips in virtually every modern smartphone, laptop, and AI accelerator. Its market share of leading-edge manufacturing exceeded 90%.

ASML and the Machine Nobody Else Can Build

Every semiconductor fab in the world depends on lithography: shining light through a mask onto a silicon wafer to print circuit patterns. The smaller the feature you want to print, the shorter the wavelength of light you need.

For decades, the industry used ultraviolet light at wavelengths of 193 nm. Shrinking below roughly 7 nm required a different approach. The solution was Extreme Ultraviolet (EUV) lithography: light at 13.5 nm wavelength, produced by firing a high-powered laser at droplets of tin plasma in a vacuum.

Building an EUV lithography machine is among the most complex manufacturing achievements in human history. The machine requires mirrors polished to atomic smoothness, a laser system generating 250,000 pulses per second, and a vacuum environment where a single dust particle would ruin every wafer. The source of EUV light must be maintained continuously, the mirrors aligned to nanometer precision, and the entire system cooled against the thermal effects of the laser.

Only one company in the world builds EUV machines: ASML, headquartered in Veldhoven, the Netherlands. Each machine takes approximately a year to build, contains parts from hundreds of suppliers across Europe, Asia, and the United States, and costs approximately $200 million. ASML ships fewer than 60 per year. Every leading-edge chip in the world — every 5 nm, 3 nm, and 2 nm processor — is manufactured on ASML equipment.

The Single-Point-of-Failure Problem

The global semiconductor supply chain has concentrated risk in ways that have no precedent in industrial history. One company (TSMC) manufactures the majority of advanced chips. One company (ASML) builds the machines that make advanced manufacturing possible. One island (Taiwan) hosts most of TSMC’s advanced fabs. A single natural disaster, a single geopolitical disruption, or a single targeted attack on these bottlenecks could halt the production of the chips that run modern aircraft, medical devices, financial systems, and military equipment. The COVID-19 pandemic’s effect on chip supply — causing automotive plant shutdowns and years-long shortages of consumer electronics — was a preview of a much larger vulnerability.

Intel’s Fall and the IDM Crisis

For most of semiconductor history, Intel was the undisputed technology leader. Its manufacturing process was consistently one generation ahead of competitors; “Intel Inside” meant not just a brand but a guarantee of cutting-edge silicon.

The cracks appeared at 10 nm. Intel announced 10 nm manufacturing in 2015; it did not ship volume production until 2019. The delays were caused by an overly aggressive density target — Intel defined “10 nm” more ambitiously than competitors — but the effect was that TSMC shipped 7 nm chips to Apple and AMD while Intel’s customers waited. AMD’s processors, manufactured at TSMC, beat Intel’s in both performance and power efficiency for the first time in a decade.

Intel’s response — returning to process leadership, rebuilding manufacturing capability, and launching an Intel Foundry Services business to compete with TSMC — represented an acknowledgment that the IDM model it had defined was under existential pressure.

The Geopolitics of Advanced Chips

The semiconductor industry’s geographic concentration became a national security concern in the early 2020s.

The United States designed the world’s most advanced chips but manufactured almost none of them domestically. China consumed approximately 60% of the world’s semiconductors but manufactured few of the advanced ones. Taiwan, a self-governing democracy that the People’s Republic of China claims as its territory, hosted the manufacturing capacity that both depended on.

The U.S. government’s response was the CHIPS and Science Act (August 2022): $52 billion in subsidies to encourage semiconductor manufacturing on American soil. Intel, TSMC, Samsung, and Micron all announced or accelerated U.S. fab construction. The European Union passed a parallel European Chips Act (2023).

Simultaneously, the U.S. imposed export controls on advanced semiconductor equipment and chips to China — blocking ASML from shipping EUV machines to Chinese customers and restricting NVIDIA’s ability to sell its most advanced AI training chips to Chinese buyers. China’s response was a multi-hundred-billion-dollar program to develop domestic semiconductor manufacturing capability.

Dead End: The Limits of Scaling

Moore’s Law is not dead, but it has changed character. Transistors at 3 nm are so small that quantum mechanical effects — electrons tunneling through barriers, thermal noise disrupting state — become significant design constraints. The power density of modern chips has reached levels where cooling is a primary design challenge. Each new process node costs more to develop and delivers less improvement than the last.

Beyond Moore: The Alternative Paths

As classical scaling slows, the industry has pursued alternatives:

3D stacking: layering multiple chips vertically (HBM memory, chiplet architectures like AMD’s 3D V-Cache)
Specialized silicon: domain-specific processors (TPUs, NPUs, DSPs) that outperform general-purpose chips in specific workloads
Advanced packaging: connecting multiple chiplets with high-speed interconnects on a single package rather than integrating everything on one die
New materials: gallium nitride, silicon carbide, and eventually carbon nanotubes as alternatives to silicon

Whether these paths together can sustain the historical rate of computing improvement — or whether a slower era of incremental progress is beginning — is the defining question of semiconductor technology in the 2020s.

For the chips that GPUs run on, see The GPU Revolution. For the integrated circuits that started this story, see The Integrated Circuit Revolution.